The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advancements to be realized, similar developments in IC processing and manufacturing are needed.
For example, it is generally desired to reduce stray capacitance among features of field effect transistors, such as capacitance between a gate structure and source/drain contacts, in order to increase switching speed, decrease switching power consumption, and/or decrease coupling noise of the transistors. Certain low-k materials have been suggested as insulator materials surrounding gate structures so as to provide lower dielectric constant (or relative permittivity) and reduce stray capacitance. However, as semiconductor technology progresses to smaller geometries, the distances between the gate structure and source/drain contacts are further reduced, resulting in still large stray capacitance. Therefore, although existing approaches in transistor formation have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.